library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity mult_PF_test is
end entity mult_PF_test;

architecture mult_PF_test_arq of mult_PF_test is

component mult_PF is
  generic(N   : natural:=32;
          EXP : natural:=8);
  port(
    clk : in std_logic;
    a   : in std_logic_vector(N-1 downto 0);
    b   : in std_logic_vector(N-1 downto 0);
    z   : out std_logic_vector(N-1 downto 0));
end component mult_PF;

constant N : natural:=32;
constant EXP : natural:=8;
signal a_test : std_logic_vector(N-1 downto 0):=(others => '0');
signal b_test : std_logic_vector(N-1 downto 0):=(others => '0');
signal z_out    : std_logic_vector(N-1 downto 0):=(others => '0');
signal clk    : std_logic:='0';
begin

   a_test <= std_logic_vector(to_unsigned(100000000,N)) after 20 ns; 
   b_test <= std_logic_vector(to_unsigned(268435456,N)) after 40 ns;

    DUT: mult_PF
    generic map(N => N, EXP => EXP)
    port map(
              clk => clk,
              a   => a_test,
              b   => b_test,
              z   => z_out);
   
    clk <= not(clk) after 10ns;

end architecture;
